Field effect transistor utilizing the gate structure two-dimensionally

Abstract

The object of the invention is a field-effect transistor comprising a drain (D) and a source (S) and a gate (G) with a determined width (W) and length (L), equipped with means (G1-G2) for generating a voltage distribution on the gate in direction of its width. The gate comprises a first end in direction of its width and a second end essentially opposite to the first end, and that a first gate contact (G1) is arranged at the first end for providing a first voltage (V.sub.G1) to the first end, and a second gate contact (G2) is arranged at the second end for providing a second voltage (V.sub.G2) to the second end, for generating a voltage distribution on the gate in direction of its width with the help of a difference voltage (V.sub.G1 -V.sub.G2) between the first (G1) and the second (G2) gate contact. On the basis of the first (V.sub.G1) and second (V.sub.G2) voltage, a determined common-mode voltage is obtained on the gate, by which the voltage level of the gate is adjusted, and the difference voltage can be used for the adjustment of the voltage distribution in the width direction of the gate. In addition, a third gate contact (G3) can be arranged on the gate for generating a determined potential (V.sub.G3) as a common voltage evenly over the entire gate area. As an output (I.sub.DS), a signal proportional to the product of the difference voltage (V.sub.G1 -V.sub.G2) and common-mode voltage is obtained from the field-effect transistor thereby forming a multiplier.