Devices and systems with parallel logic unit operable on data memory

Abstract

A data processing device includes a first memory for storing data, a second memory for storing instructions and circuitry connected to the first memory for electronically performing computation operations. Registers temporarily hold digital signals representative of first values on which computations are based and second values that are computed. Address decoding circuitry has an input connected to an address bus. The address decoding circuitry has outputs connected to the registers to decode addresses from the address bus and access the registers. A control circuit is connected to the second memory and responds to at least one of the instructions for sending an address via the address bus to the address decoding circuitry to transfer a value in a first one of the registers directly to a second one of the registers thereby bypassing the first memory during the transfer. Other devices, systems and methods are also disclosed.