The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 1998
Filed:
Jul. 15, 1997
Yasuhiro Fujii, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A semiconductor memory with hierarchical bit lines has a plurality of local bit lines, a plurality of global bit lines, a plurality of word lines, a plurality of memory cells each arranged at a connection portion between each local bit line and each word line, and a plurality of transfer gates. The local bit lines are connected to the global bit line through the transfer gates, which are arranged around the centers of the local bit lines. Further, the semiconductor memory has a dummy bit line portion having a dummy bit line that is charged up to a precharging reference voltage during a standby period and is set to a floating state during an active period, to provide the sensing reference voltage. In addition, the semiconductor has sense amplifiers each being formed in an area matching with the interval of a given number of the global bit lines and each receiving signals from a pair of the global bit lines arranged on both sides thereof.