Sense amplifier circuit with minimized clock skew effect

Abstract

A sense amplifier with improved compensation for clock skew effects is provided and includes a sense amplifier enabling mechanism for receiving first and second control signals. The sense amplifier further includes a first logic mechanism for providing the first control signal to a first input of the sense amplifier enabling mechanism, and a second logic mechanism for providing the second control signal to a second input of the sense amplifier enabling mechanism, wherein the first and second logic mechanisms reduce speed degradation by minimizing skew between the first and second control signals. In a method aspect, a method for reducing speed degradation in a sense amplifier includes providing a pull down device, and coupling the pull down device to first and second signal paths, the first signal path propagating a first clock signal and the second signal path propagating a second clock signal, for reducing speed degradation resulting from skew between the first and second clock signals. The method further includes providing the first signal path to a gate of the pull down device and providing the second signal path to a source of the pull down device.