The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 1998

Filed:

Jan. 13, 1997
Applicant:
Inventors:

Gary W Jones, Lagrangeville, NY (US);

Susan K Jones, Lagrangeville, NY (US);

Jeffrey Marino, Fishkill, NY (US);

Joseph K Ho, Wappingers Falls, NY (US);

R Mark Boysel, Pleasant Valley, NY (US);

Steven M Zimmerman, Pleasant Valley, NY (US);

Yachin Liu, Poughkeepsie, NY (US);

Michael J Costa, Poughkeepsie, NY (US);

Jeffrey A Silvernail, Kingston, NY (US);

Assignee:

FED Corporation, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01J / ;
U.S. Cl.
CPC ...
313336 ; 313309 ; 313310 ; 313351 ; 3151691 ; 3151692 ; 3151693 ; 3151694 ; 445 24 ; 445 50 ;
Abstract

A field emitter device includes a column conductor, an insulator, and a resistor structure for advantageously limiting current in a field emitter array. A wide column conductor is deposited on an insulating substrate. An insulator is laid over the column conductor. A high resistance layer is placed on the insulator and is physically isolated from the column conductor. The high resistance material may be chromium oxide or 10%-50% wt % Cr+SiO. A group of microtip electron emitters is placed over the high resistance layer. A low resistance strap interconnects the column conductor with the high resistance layer to connect in an electrical series circuit the column conductor, the high resistance layer, and the group of electron emitters. One or more layers of insulator and a gate electrode, all with cavities for the electron emitters, are laid over the high resistance material. One layer of insulator is selected from a group of materials including SiC, SiO, and Si.sub.3 N.sub.4. An anode plate is attached with intermediate space between the anode plate and the microtip electron emitters being evacuated.


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