The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 1998
Filed:
Nov. 06, 1997
Wen-Chau Liu, Tainan, TW;
Shiou-Ying Cheng, Tainan, TW;
National Science Council, Taipei, TW;
Abstract
A new high-speed resonant tunneling device, namely, a long-period superlattice resonant tunneling transistor, is developed according to the invention. The structure of the proposed 20-period superlattice resonant tunneling transistor consists of an InP substrate, a buffer layer formed by GaInAs material on the substrate, a collector layer formed by GaInAs material on the buffer layer, a base layer formed by GaInAs material on the collector layer, an emitter layer formed by GaInAs material on the base, a 20-period superlattice resonant tunneling layer formed by AlInAs and GaInAs materials on the emitter layer, and an ohmic contact layer formed by GaInAs material on the 20-period superlattice resonant tunneling layer. Furthermore, the emitter region includes a 20-period AlInAs/GaInAs superlattice and an emitter layer. Due to the presence of an emitter-base homojunction, collector-emitter offset voltage (V.sub.CE,offset) can be reduced significantly. In addition, the valence band discontinuity (.DELTA.Ev) at the AlInAs/InGaAs heterojunction may be used as a barrier for holes injected from the base toward the emitter region. Therefore, the emitter injection efficiency and current gain can be increased. From the theoretical analysis and computer simulation, two subbands are observed in the superlattice region. Under the proper applied bias, the studied device will create n-type negative differential resistance (NDR). Consequently, the proposed device shows good promise for use in amplification, parity generator, and multiple-value logic circuit applications.