Semiconductor integrated circuit

Abstract

The present invention intends to provide a semiconductor device integrated circuit having an additive circuit capable of the evaluation of the dynamic performance of a memory block in a mixed logic and memory IC or a high-speed logic block in a semiconductor device integrated circuit, directly from the outside of the device. In order to evaluate the dynamic performance of the memory block or the high-speed logic block by using a tester, the device is provided on the chip with bus lines which bypass the peripheral logic and are connected to the input terminals of the memory block or the high-speed logic block. In the device, the delay time difference between the bus lines are measured from the outside of the device, at first. By use of the measurement result, the timing error of inputting a plurality of test pulse signals used for the dynamic performance evaluation is compensated. A switching element is provided between the reference line and each of the bus lines. A delay time measuring signal is input to each of external I/O pads connected to the bus line through which the delay time of the signal passing is measured, and then the differences in the delay time of all the bus lines are obtained on the basis of the signal delay time produced between the reference line and the each of the line. By use of the difference in the delay time of the lines, the input timing error when the memory block is measured with the tester is compensated, thereby precise evaluation of the memory block or the high-speed logic block is obtained.