Method and a system for specifying and automatically analyzing multiple

Abstract

In a computer aided design system for assisting in the design and analysis of integrated circuits, users can specify an integrated circuit using either a conventional circuit component netlist, or an HDL circuit description. Timing constraints are specified using conventional system level timing constraints, at least one clock timing constraint and a plurality multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of the clock based timing constraints concern timing constraints for duration longer than a single clock period. In addition, the user may provide the system with a plurality of constraint based timing path specifications, each indicating signal paths through the integrated circuit to which specified ones of the multi-cycle timing constraints are applicable and signal paths to which the specified ones of the multi-cycle timing constraints are not applicable. The computer aided design system then automatically verifies that the integrated circuit satisifies the specified timing constraints. During the timing constraint verification process, for mutli-clock timing constraints, signal arrival times and required signal arrival times are propagated and back-propagated only through signal paths consistent with the constraint based timing path specifications. In addition, the verified netlist, timing constraints and constraint based timing path specifications may be passed to a silicon compiler for automatically placing/routing a circuit in accordance with the netlist, timing constraints and constraint based timing path specifications.