The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 1998

Filed:

Apr. 07, 1997
Applicant:
Inventors:

David J Anderson, Scottsdale, AZ (US);

Robert M Gardner, Gilbert, AZ (US);

Jerald A Hallmark, Gilbert, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
341120 ; 341118 ; 341144 ; 341133 ;
Abstract

A ferroelectric transistor (72) is programmed with a gate voltage that shifts a threshold voltage of the ferroelectric transistor (72). The shifted threshold voltage generates a correction current (.DELTA.I.sub.(N-1)) in a combination circuit (52) that trims an output voltage of a DAC trim circuit (50). A ferroelectric material (32) of the ferroelectric transistor (72) stores a charge in accordance with a programming voltage and allows a dynamic adjustment of the correction current (.DELTA.I.sub.(N-1)) that is used to modify the output voltage of the DAC trim circuit (50).


Find Patent Forward Citations

Anderson, David. (1998). Digital-to-analog converter and method of calibrating (U.S. Patent No. 5825317). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5825317

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…