The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 1998

Filed:

Nov. 25, 1996
Applicant:
Inventor:

Remo J D'Ortenzio, Rochester, NY (US);

Assignee:

Xerox Corporation, Stamford, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
341 65 ; 341 67 ;
Abstract

A low cost, high speed, JPEG Huffman code decoder. The entire gamut of Huffman codes is partitioned into groups, with each group being associated with it's own small look up table to minimize the overall memory requirements. The current Huffman code is stored in a register. For the disclosed embodiment there are N=4 memories with sizes 128, 256, 128 and 256 elements respectively. For the specific typical Huffman code set cited, the partitioning is: The code words in the first group have 7 bits or less and are decoded in the first memory. The next group has from 5 to 7 leading ones, where the first five 1's are masked out and the remaining bits are used to address the second memory. The remaining codes have at least eight leading ones. Here, the first eight ones are masked out and the remaining bits are used to address the last memory. (In this example, one of the memories is not used). Finally, the first eight bits are used in a selector to enable the correct memory so that a single correct output data word is output. The disclosed N=4 embodiment is designed to handle any custom JPEG Huffman code set. This concept can be extended to other memory partitions (a N=6 example is cited) that might provide some desirable memory vs logic switching tradeoffs.


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