Low voltage dmos transistor

Abstract

A method of fabricating a semiconductor device containing a HVDMOS transistor and a LVDMOS transistor and the device which includes providing a region of semiconductor material of a first conductivity type and forming a high voltage DMOS transistor disposed in the region. A relatively low voltage DMOS transistor is also disposed in that region and electrically isolated from the high voltage DMOS transistor. The low voltage DMOS transistor has spaced apart source and drain regions disposed in the region of semiconductor material and a back gate region of the first conductivity type disposed in the region of semiconductor material between the source and drain regions. The back gate region is electrically coupled to the region of semiconductor material. The region of semiconductor material includes a surface, the source, drain and back gate regions extending to that surface. A well of second conductivity type opposite to the first conductivity type is provided in the region of semiconductor material and the high voltage DMOS transistor is disposed in that well. Optionally, one only of the source or drain regions of the low voltage DMOS transistor is disposed in the well. Also, optionally, a region of second conductivity type opposite to the first conductivity type can be provided between the back gate region and the drain region which is less highly doped than the drain region.