The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 1998
Filed:
Dec. 12, 1996
Ching-Nan Yang, Hsinchu, TW;
Mosel Vitelic Inc., Hsinchu, TW;
Abstract
A method of making a complementary metal oxide semiconductor field effect transistor (CMOSFET) using liquid phase deposition. At first, a P-type silicon substrate is prepared, on which are formed a field oxide layer, a P-well, an N-well and a gate oxide layer. Next, a first polysilicon layer is formed. After doping the first polysilicon, a tungsten silicide layer is formed on the first polysilicon layer. Then, the first polysilicon layer and the tungsten silicide layer are patterned to form the polycide gate electrodes. With a mask shielding the area designated to be the N-channel FET, a P.sup.- type ion implant is performed. Then, a first silicon dioxide layer is formed by liquid phase deposition, followed by an anisotropic etching to form the first sidewall spacers. Then, a P.sup.+ type ion implant is performed. A second silicon dioxide layer is again formed by liquid phase deposition. Now, after removing the mask, an N.sup.- type ion implant is performed using the second silicon dioxide layer as a mask. Next, the second sidewall spacers are formed by depositing and etching back a layer of tetraethoxysilanes dielectric layer. Then, an N.sup.+ type ion implant is performed to form the N.sup.+ doped areas. After a boronphosphosilicate glass layer is deposited on the field oxide layer, the second silicon dioxide layer and the device area, the CMOSFET is completed.