The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 1998

Filed:

Jun. 28, 1996
Applicant:
Inventors:

Anilkumar Chinuprasad Bhatt, Johnson City, NY (US);

Donald Herman Glatzel, New Milford, PA (US);

Allen F Moring, Vestal, NY (US);

Voya Rista Markovich, Endwell, NY (US);

Kostas Papathomas, Endicott, NY (US);

David John Russell, Apalachin, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K / ;
U.S. Cl.
CPC ...
29832 ; 29830 ; 29840 ; 29852 ; 29837 ; 174262 ; 174263 ; 427 97 ;
Abstract

Circuit boards are manufactured by forming a substrate with a dielectric surface, laminating a metal foil and a peelable film to the substrate, and forming holes in the substrate through the peelable film and foil. A filler material with an organic base may be filled with electroconductive particles or dielectric thermoconductive particles. The filler material is laminated onto the peelable film with sufficient heat and pressure to force the filler material to fill the holes. For thermoconductive filler the holes are filled sufficient for electrical connection through the holes. The filler material is abraded to the level of the foil and is then copper plated. The copper is patterned to form a wiring layer. A permanent dielectric photoresist layer is formed over the wiring layer and via holes are formed through the photoimageable dielectric over pads and conductors of the wiring layer. Holes are formed through the substrate and the photoimageable dielectric, walls of the via holes, and walls of the through holes are copper plated. The copper plating on the photoimageable dielectric is patterned of form an exterior wiring layer. Components and/or pins are attached to the surface of the circuitized substrate with solder joints to form a high density circuit board assembly.


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