Dual port random access memory matching circuit for versa module europe

Abstract

A dual port random access memory (RAM) matching circuit for a Versa Module Europe bus (VMEbus) which makes it possible to have a higher capacity when transmitting and receiving data by using a RAM which is possible to bidirectionally access during a communication between processors using a VMEbus of an electronic switching system. The dual port RAM matching circuit includes a dual port RAM for bidirectionally outputting/inputting a data in accordance with an address and a control signal, an address matching unit for selecting first through sixteenth addresses from a local system or first through sixteenth addresses from a VMEbus in accordance with the control signal, and a data matching unit for selecting 0-th through thirty first CPU data or 0-th through thirty first VMEbus data from the local system in accordance with the control signal from the control bus, and for checking a parity during a data transmission and receiving operation. The dual port RAM matching circuit further includes a control signal matching unit for selecting either the control signal from the local system or the control signal from the VMEbus in accordance with the control signal from the control bus and for outputting the selected control signal to the control bus, and a control signal generator for receiving an address information signal and a clock signal from the local system, and an address information signal from the VMEbus, and outputting control signals to the control bus.