The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 1998
Filed:
Feb. 16, 1996
Steven G Morton, Oxford, CT (US);
Other;
Abstract
The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single, pipelined instruction unit that controls the operation of four, 16-bit vector processors in parallel with one group of bits, and the operation of a 24-bit scalar processor with another group of bits. Thus five instructions are typically executed for every instruction word as a result of the parallel architecture. A single, linear, 16 MB, memory address space is used, simplifying program development. The storage of 8- and 16-bit operands for use by the vector processors is supported to maximize memory utilization. The Parallel DSP Chip is specifically designed to support an enhanced C compiler and has two software stack pointers, one for the vector processors and one for the scalar processor, plus an interrupt stack pointer. The Parallel DSP Chip executes a single task in parallel. Using an enhanced C compiler, simple, familiar, scalar processing programming techniques can be used, and a simple, single-task operating system can be used for software development. The basic programming concept is to define one or more arrays of four-element structures using the enhanced C compiler. One element in such a structure is provided for each of the four vector processors. The structure to be processed at any one time is selected by an address computed by the scalar processor. The same operation is applied to all of the elements of the structure by the simultaneous operation of the vector processors. To access the next structure in an array of structures, the scalar processor advances the address by the number of bytes in the structure.