Pipelined processor for executing repeated string instructions by

Abstract

A pipelined processor is modified to efficiently process repeated string instructions. A repeated string instruction repeats an iteration a number of times determined by a counter variable stored in a register file. Each iteration includes at least three pipeline flows to perform a load, store, or compare of a character in the string, and to decrement the counter variable. When the last flow of an iteration reaches the execute stage near the end of the pipeline, the current value of the counter variable is compared to the maximum number of iterations which may be present in the pipeline at one time. When the counter variable is equal to the maximum number of iterations, the execute stage signals the decode stage to stop dispatching iterations. The iterations in the pipeline are completed, providing the proper number of iterations. For short strings, the counter value may be less than the maximum number of iterations, and this is signaled to the decode stage, which flushes the pipeline once the current iteration completes. The decode stage does not need a copy of the counter variable, reducing dedicated hardware for processing repeated string instructions.