Split data path fast at-bus on chip circuits systems and methods

Abstract

A computer system has an integrated circuit including a single-chip integrated circuit including an external-to-internal bus interface circuit coupled to external pins for connection to an external bus, and an on-chip internal bus coupled to the external-to-internal bus interface circuit and having a plurality of at-least-sixteen bit data paths including first and second such data paths. A parallel port on-chip is coupled to the on-chip internal bus and to both the first and second data paths therein. An interface circuit is coupled between the first and second data paths, wherein the first data path is connected to reflect the state of external inputs to the on-chip internal bus and of any internally generated second data path outputs to be sent externally, and wherein when the second data path carries internally generated signals to internal destinations, the states of the first and second data paths differ. Other circuits, systems and methods are also disclosed.