Phase recovery circuit for high speed and high density applications

Abstract

A phase recovery circuit consists of a tapped delay line created by a string of inverters where taps are taken at every other inverter. To initialize the circuit, each tap loads a signal sample into a holding register where the holding register consists of a flip-flop connected to each tap. The flip-flops are loaded by the active edges of the system clock such that each flip-flop contains a sample of data at a given point in time. The sample register delivers the data to a processor that periodically creates histograms of the signal to determine the signal transition points between adjacent bits and the number of taps between the transition points that define a bit. Once the transition points are known, the center of the bit to be latched is located and the tap nearest the center of the bit is used to latch the data for delivery to the next downstream location. From the histograms the processor can also determine if the signal is shifting relative to the system clock. If the signal shifts, the processor selects another tap, located nearest the new location of the center of the bit, and latches the data from the new tap. The system also uses an elastic store downstream from the tapped delay line to preclude the need for an extremely long delay time which would cause signal degradation