The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 1998
Filed:
Apr. 02, 1996
Daniel Watkins, Saratoga, CA (US);
Satish Venugopal, Santa Clara, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A random verification environment for verifying a semiconductor device includes a hardware engine programmed to include a random input generator that builds a set of test vectors. A first memory connected between the hardware engine and the semiconductor device stores the set of test vectors and supplies the set of vectors to the semiconductor device under the control of a first state machine generated by the hardware device. A second memory connected to the semiconductor device receives output signals from the semiconductor device in response to input test vectors. A random test iterator in the hardware engine provides a first state machine and also provides a second state machine that writes the signals output from the semiconductor device to the second memory. The test vectors are input to the semiconductor device at a rate equal to the operating rate of the semiconductor device. An expected output generator is arranged to receive the test vectors from the first memory. An output comparator is arranged to receive outputs from the expected output generator and from the second memory and to record whether the output of the semiconductor device for each test vector is the expected output provided by the expected output generator.