Phase locked loop ciruit for a liquid crystal display

Abstract

This single voltage controlled oscillator for a PLL circuit has two control loops: a low noise ration is maintained by a main loop; while a wide frequency capture range is ensured by a sub-loop controlled by a one-chip microcomputer. The main control loop is a low gain loop with a narrow capture range that compares the phase of the output of the PLL circuit with the phase of a horizontal synchronous video signal supplied to a LCD display. The sub-loop is a high gain loop with a broad frequency range that includes a processor that monitors the lock on the main loop. When the lock is broken, the processor increments or decrements the voltage supplied to this sub-loop in one or more steps until the lock is reestablished, and the PLL circuit is again operating within the narrow capture range of the low gain loop.