Circuit for cancelling the dc offset in a differential analog front end

Abstract

An analog front end for signal processing circuit such as a hard-disk data read channel having a calibration circuit for canceling DC offset is described. First, the DC offset is cancelled from a positive phase input to an A/D converter (ADC). Second, a DC offset is cancelled separately from a negative phase input to the A/D converter. The combined positive and negative phases form an amplified analog signal that is used as the differential input to the A/D converter. Finally, the DC offset in a path that encompasses the system analog input through the system digital output is cancelled. Controlling the buffer amplifier bias makes trimming unnecessary. It also enables faster calibration. Further, the two differential phase lines, i.e., the positive phase line and the negative phase line, are each calibrated in turn. As such, a common calibration circuit may be used, thereby avoiding circuit duplication.