The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 1998

Filed:

Oct. 13, 1995
Applicant:
Inventors:

Kazumi Yamaguchi, Tokyo, JP;

Takao Arai, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257355 ; 257173 ; 257368 ;
Abstract

A semiconductor device has a vertical MOS FET and a trigger element connected between the drain and the gate of the MOS FET. The trigger element has a heavily doped n region, a lightly doped p region and a lightly doped n region. The trigger element has a breakdown voltage lower than the drain-to-source rated voltage of the MOS FET and exhibits a negative resistance characteristic. A surge voltage enterring the drain of the MOS FET raises the gate potential of the MOS FET by flowing through the trigger element to thereby trigger the source-drain path of the MOS FET. The negative resistance characteristic of the trigger element enables to lower the temperature rise of the MOS FET to thereby protect the MOS FET against thermal destruction. A bidirectional diode set may be connected in series to the trigger element to design various breakdown voltage of the protective path.


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