Reduced power tuner chip with integrated voltage regulator for a

Abstract

An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip has reduced-power features which allow the incorporation of an on-chip voltage regulator. The tuner chip is a direct conversion tuner with on-chip tuning frequency generation and reduced power interface signals. The on-chip voltage regulator provides a constant power supply for nonlinear components of the tuner and frequency generation circuitry to minimize phase noise. Broadly speaking, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip includes an on-chip voltage regulator, in addition to a tuning oscillator, a charge pump, a downconverter, and a lowpass filter. The on-chip voltage regulator is operable to provide a stable power supply to the tuning oscillator and the charge pump. The tuning oscillator is coupled to a tank circuit having an adjustable resonance frequency, and the charge pump is coupled to the tank circuit to control the resonance frequency. The downconverter receives a tuning frequency provided by the tuning oscillator, receives a receive signal, and combines the tuning frequency signal with the receive signal to produce a product signal. The lowpass filter acts to convert the product signal into a baseband signal, which may then be provided as a differential output signal.