Single clock cycle data compressor/decompressor with a string reversal

Abstract

A single clock cycle adaptive data compressor/decompressor with a string reversal mechanism is described which can perform data compression and decompression at the rate of one uncompressed symbol per clock cycle. The LZW data compression algorithm has been improved for use in this data compressor. The compressor builds a string table as the data is received. Each string within the table is made up of the address within the table of the longest previously seen matching string and the one character that makes this string different. This data compressor/decompressor utilizes a content addressable memory to store the string table. This content addressable memory allows the compressor to store the current symbol string in a table while that same string table is simultaneously searched for the current string. During decompression the characters within a symbol string are output in reverse of the order in which they were input. In order for the data to be restored to its original format the characters within a string must be reversed before they are output. Two dual-ported random-access memories are used as circular queues to perform this string reversal. These dual-ported random-access memories have the capability to output the characters within a string from the string reversal mechanism in the order that they were input. The first dual-ported random access memory is used to store the strings of symbols to be reversed and the second dual-ported random access memory is used to store the addresses of the first and last symbol of each string that is stored in the first dual-ported random-access memory.