The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 1998

Filed:

Jan. 19, 1996
Applicant:
Inventors:

Yasushi Mori, Higashiyamato, JP;

Naoki Ozawa, Akishima, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J / ;
U.S. Cl.
CPC ...
370532 ; 370536 ; 370537 ;
Abstract

A digital signal transmission system operates in a mode for transmitting multiplexed signals as a serial digital signal and in a mode for transmitting only a predetermined signal. A transmitter of the system includes a first control circuit which, in a particular signal transmission mode, places only a particular signal processing circuit block for transmitting a particular signal in an operative state and places in an inoperative state a multiplexer circuit block for multiplexing the predetermined signal with at least one other signal. In a multiplexed transmission mode, the first control circuit places in an operative state only the multiplexer circuit block and places in an inoperative state the particular signal processing circuit block. A receiver of the system includes a second control circuit which, in a particular signal transmission mode, places a particular signal restoring circuit block for restoring the transmission signal received through the transmission path to an operative state and places in an inoperative state a demultiplexer circuit block. In an multiplexed transmission mode, the second control circuit places in an operative state only the demultiplexer circuit block, which demultiplexes a multiplex signal received through the transmission path into a plurality of digital signals, and places into an inoperative state a particular digital signal restoring circuit block.


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