The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 1998
Filed:
May. 30, 1997
Applicant:
Inventors:
Tohru Kimura, Kanagawa, JP;
Charles G Sodini, Cambridge, MA (US);
Assignees:
NEC Corporation, Kanagawa, JP;
Massachusetts Institute of Technology, Cambridge, MA (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36523003 ; 365233 ;
Abstract
In a logic integrated DRAM LSI with SIMD architecture, a intentional clock skew is introduced for both between DRAM blocks and between logic blocks due to reduce the magnitude of peak current, operation frequency and number of I/O are defined for both DRAM blocks (frequency f.sub.M, I/O number m) and logic blocks (frequency f.sub.N, I/O number n) to keep the relation of
Kimura, Tohru. (1998). Circuit technique for logic integrated dram with simd architecture and a (U.S. Patent No. 5818788). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5818788
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