Automatic mode selection circuit for semiconductor memory device

Abstract

An automatic mode selection circuit for automatically selecting low voltage transistor transistor logic and high-speed input/output interface modes in a semiconductor memory device. The automatic mode selection circuit comprises an external reference voltage pad for delivering an external reference voltage, an internal reference voltage generator for generating an internal reference voltage, a power-on detector for detecting a power-on time point and then generating a pulse signal for a predetermined time period, a switching circuit for switching the external reference voltage from the external reference voltage pad and the internal reference voltage from the internal reference voltage generator in response to an output signal from the power-on detector, a reference voltage detector connected between the external reference voltage pad and the switching circuit for detecting the external reference voltage from the external reference voltage pad, a comparator for comparing an output voltage from the reference voltage detector with the internal reference voltage from the internal reference voltage generator in response to the output signal from the power-on detector, and a latch circuit for latching an output signal from the comparator and supplying the latched signal to an output terminal.