Small, fast cmos 4-2 carry-save adder cell

Abstract

A CMOS 4-2 carry-save adder cell implementation. A XNOR gate is used in the computation of SUM and CARRY. By using an XNOR gate, there are no possible input permutations which will cause any output in the SUM logic to be driven by two P-channel devices in series. The final XOR function needed to compute the SUM output is performed by a 2-to-1 multiplexor and two inverters. The maximum resistance from input to output of the 2-to-1 multiplexor is relatively low, and the worst case is when the CIN input drives through the transmission gate. The input capacitances are very low. The maximum load driven by the output is low because the output never drives through the drains of any transistors. Instead, the output drives only the gates of four transistors to implement the XOR function. A single 8-transistor complex gate and an inverter are used to calculate COUT. The transistors in the complex gate can be made relatively small, thus minimizing the input capacitance. A complex gate is used to implement the logic function .about.((IN0 & IN1)+(IN2 & IN3)). The output of this complex gate is double buffered using two inverters. Minimum size transistors for the complex gate further minimize the input capacitances and reduce the area needed to lay out the gate. All the outputs are driven by final inverters to provide strong, clean outputs.