The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 1998
Filed:
Aug. 01, 1997
Hiroshi Takahashi, Ohi-machi, JP;
Shigeshi Abiko, Tokyo, JP;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Clock signal generating circuit for preventing occurrence of clock skew, totally preventing through current, and readily controlling the clock, which includes a master clock signal generating circuit 2M and a slave clock signal generating circuit 2S. The master clock signal generating circuit 2M generates a master clock signal MCLK at a high level based on a slave clock signal SCLK at a low level and a clock signal CLK at a low level, and generates a master clock signal MCLK at a low level based on the clock signal CLK at a high level. The slave clock signal generating circuit 2S generates a slave clock signal SCLK at a low level based on the clock signal CLK at a low level and a slave clock signal SCLK at a high level based on the master clock signal MCLK being at a low level and the clock signal CLK at a high level. A master clock delay generating circuit 3M inputs the slave clock signal SCLK as output from the slave clock signal generating circuit 2S to be able to set the delay time optionally in the master clock signal generating circuit 2M by delaying for the necessary time. Additionally, a slave clock delay generating circuit 3S is provided which inputs the master clock signal MCLK output from the master clock signal generating circuit 2M to be able to set the delay time optionally into the slave clock signal generating circuit 2S by delaying for the necessary time.