The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 1998
Filed:
Jun. 11, 1996
Amos Intrater, Netanya, IL;
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
Apparatus and method for testing the connection (i.e. solder joint) between an input/output (I/O) pin of an integrated circuit and a conductive trace of a printed circuit board (PCB). The internal circuitry of the integrated circuit is isolated from each I/O pin, and a first voltage source is coupled to each I/O pin via a respective pull-up load resistor. A tester circuit is coupled to each conductive trace of the PCB and compares the voltage V.sub.T thereon with a high threshold level (HTVL) and a low threshold level (LTVL) to test for a proper connection. Voltage V.sub.T is derived for an I/O pin under test when a resistive element, which is part of the tester circuit, is operatively coupled between the corresponding conductive trace and a second voltage source. If V.sub.T is below the LTVL or above the HTVL, the I/O pin is improperly coupled to the conductive trace. If V.sub.T is between the LTVL and HTVL, then the voltage on each of the other traces is compared to the HTVL. If the voltage level of one of the other traces not under test is below the HTVL, then the other I/O pin is electrically shorted to the I/O pin under test.