The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 1998

Filed:

Feb. 29, 1996
Applicant:
Inventors:

Robert B Davies, Tempe, AZ (US);

Andreas A Wild, Scottsdale, AZ (US);

Diann M Dow, Chandler, AZ (US);

Peter J Zdebel, Mesa, AZ (US);

E James Prendergast, Phoenix, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257506 ; 257510 ; 257377 ;
Abstract

A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60, 97) that can be used to transport electrical signals across the device (10).


Find Patent Forward Citations

Davies, Robert. (1998). Semiconductor device having a pedestal (U.S. Patent No. 5818098). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5818098

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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