The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 1998
Filed:
Dec. 10, 1997
Shye Lin Wu, Hsinchu County, TW;
Acer Semiconductor Manufacturing Inc., Hsichu, TW;
Abstract
A semiconductor processing method for forming self-aligned T-gate Lightly-Doped Drain (LDD) device of recessed channel is presented. The method comprises the steps of covering a substrate with pad oxide, forming a lightly-doped layer by ion implantation, depositing a silicon nitride layer on the surface of the pad oxide, and etching the silicon nitride layer according to a predefined mask pattern to expose the silicon oxide layer and to form a gate region. A polysilicon spacer region is formed on the side-walls of the silicon nitride layer. Anisotropic etch is used to etch the polysilicon spacer region, and at the same time etch the exposed pad oxide and a portion of the substrate to form a T-shaped groove. An amorphous silicon layer is deposited in the T-shaped groove after forming a thin oxide layer, then the amorphous silicon deposited apart from the T-shaped groove region is removed. The silicon nitride layer is removed to form a T-gate. Ion implantation is used to form a heavily-doped source/drain, and finally metal contacts are formed on the polysilicon T-gate and the heavily-doped source/drain regions.