Method of manufacturing a semiconductor memory device including memory

Abstract

A method of manufacturing a semiconductor memory device having a plurality of memory cells arranged in matrix includes forming a first masking layer on a semiconductor substrate of a first conductivity type and patterning the first masking layer to form a plurality of parallel strips which extend in first direction. A second masking layer is formed on the patterned first masking layer and the second masking layer is patterned to form a plurality of parallel strips which extend in a second direction perpendicular to the first direction. First impurities of a second conductivity type are implanted into the semiconductor substrate, using the patterned first and second masking layers as a mask, to form impurity regions of the second conductivity type. The patterned second masking layer is then removed and an insulating film is formed in the spaces between the parallel strips of the patterned first masking layer for isolating element regions on the semiconductor substrate. The insulating film covers the impurity regions of the second conductivity type. The patterned first masking layer is then removed and a conductive layer is patterned to form control gates for the memory cells in the element regions on the semiconductor substrate. Second impurities of the second conductivity type are implanted into the semiconductor substrate using the control gates as a mask to form self-aligned source regions for the memory cells, wherein the source region of a first memory cell is connected to the source region of a second memory cell by one of the impurity regions of the second conductivity type.