The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 1998
Filed:
Oct. 09, 1996
Gregory S Averill, Fort Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A system and method for testing and verifying the correctness of cache accesses on a model or implementation of a processor that performs speculative and or out-of-order instruction execution. For each behavioral model of a processor under test in a simulation system, an architectural model is created that is fed the same instruction stream and system bus stimulus. The architectural model is capable of correctly and independently executing the instruction stream. The cache and TLB state of the architectural model are kept synchronous with those of the behavioral model under test. Cache synchronization is achieved by reporting, matching and verifying all speculative cache activity and all out-of-order cache accesses, move-ins and move-outs by the behavioral model as it occurs rather than in natural program order.