Apparatus and method for simulating domino logic circuits using a

Abstract

A domino logic simulator for a CMOS domino logic circuit seeds all logic circuits under test with an 'X' state before initialization of a special simulator machine cycle devoted to validating all pre-charge circuits in each stage of the CMOS domino logic circuit. In the special machine cycle, each stage of the circuit receives a discrete clock signal which is applied to the pre-charge and logic devices in precharge and evaluation phase sequences. The clock phase sequences in each stage propagate the 'X' state at each logic circuit through the succeeding stages to provide an 'X' output for the machine cycle, except a '0' state is provided as an output at the end of the machine cycle if the precharge circuit in each stage is functioning properly during the precharge sequences of the clock cycle applied to the stage. A clocked delay reset circuit in each stage provides the output of the stage. A static logic device in each stage saves power in transferring the output of a stage to a succeeding stage. A clocked buffer in each stage receives the propagated output from the previous stage for processing in the buffer stage. After pre-charge validation, a sequence of test patterns to the domino logic circuits occurs without testing the pre-charge circuit after each phase of the machine circuit.