The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 1998
Filed:
Sep. 13, 1995
NEC Corporation, Tokyo, JP;
Abstract
A configuration simulating method for a layer deposited on a silicon wafer comprising the steps of: (a) generating a string of modeling data, obtained by connecting coordinate points on a contour of a section, wherein the section is obtained by cutting a plane perpendicular to an open surface of a cylindrical contact hole, for modeling a configuration of said cylindrical contact hole formed within said silicon wafer; (b) extracting flux vectors, flowing into a predetermined one of said coordinate points on the string of modeling data, by analyzing a flux vector of particles to be deposited on said silicon wafer, wherein said particles are present in a gas phase; (c) deriving an intersection of the straight line extended from said coordinate point in the direction of said flux vector; (d) judging whether said flux vector becomes null due to a shadow effect related to said cylindrical contact hole; (e) moving from said predetermined one of said coordinate points to another of said coordinate points corresponding to the projection of said flux vector on the plane, when said flux vector is judged as not becoming null; (f) repeating steps (a) through (e) until all of the flux vector flowing into said coordinate point has been extracted; and (g) repeating steps (a) through (e) until all coordinate points have been selected.