The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 1998

Filed:

Sep. 23, 1996
Applicant:
Inventors:

Gohiko Uemura, Tokyo, JP;

Jun Yoshida, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327202 ; 327185 ; 327199 ; 327200 ; 327201 ;
Abstract

Disclosed herein is a flip/flop circuit of a master-slave type including master side and slave side latch/hold circuits 1 and 2 each being of an ECL vertical 1-step construction, first and second bias circuits 3 and 4 for biasing current sources Tr's 21 to 24 of these latch/hold circuits 1 and 2 and a control circuit 5 for pull-down controlling these first and second bias circuits 3 and 4 by clock signals. The current sources Tr's 21 to 24 are thus selectively rendered conductive and non-conductive to perform a flip-flop operation on a low power source voltage such as 1V or less.


Find Patent Forward Citations

Uemura, Gohiko. (1998). Flip-flop circuit operating on low voltage (U.S. Patent No. 5815019). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5815019

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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