The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 1998
Filed:
Mar. 18, 1996
Ewald Michael, Haar, DE;
Siemens Aktiengesellschaft, Munich, DE;
Abstract
A board includes two integrated circuits each having first terminals, second terminals, one basic configuration and one test configuration. The basic configurations contain components performing functions during normal operation of the circuits for which a particular circuit is intended. Each of the basic configurations has inputs and outputs connected to the terminals. Each of the test configurations has inputs and at least one output. Each of the inputs is connected to a respective one of the first terminals for supplying test signals to the test configuration, during a test mode of each of the circuits. The outputs are connected to the second terminals for transmitting result signals from the test configuration to the second terminals. The test and result signals are unaffected by the basic configurations during application of the test and result signals. First board contact surfaces are connected to the first terminals, for applying the test signals to the first board contact surfaces having an electrical connection with a respective one of the first terminals to be tested. Second board contact surfaces are connected to the second terminals, for picking up the result signals. A first terminal of both of the circuits is electrically connected together for simultaneously testing through the first board contact surfaces. The second terminals associated with the first terminals through the test configurations are electrically separated from one another.