The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 1998
Filed:
Jan. 09, 1997
Chika Nakajima, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A fabrication method of a semiconductor device that makes it possible to reduce the number of necessary process steps. After an insulating layer is formed on a semiconductor substructure, a polysilicon layer is formed on the insulating layer. Then, dopant atoms are implanted into the polysilicon layer so that the peak depth of the distribution of the implanted dopant atoms is located at approximately the middle level of the polysilicon layer. The implanted polysilicon layer is subjected to a heat-treatment to thereby form a dielectric region at the middle level of the polysilicon layer due to reaction of the implanted dopant atoms with silicon atoms existing in the polysilicon layer. The remaining lower and upper parts of the polysilicon layer form lower and upper polysilicon regions, respectively. Subsequently, the implanted and heat-treated polysilicon layer is patterned to have a predetermined shape. As the dopant atom to be implanted, oxygen (O) and/or nitrogen (N) is preferably used. The dielectric region is made of SiO.sub.x for oxygen only, of SiN.sub.x for nitrogen only, and of SiNO.sub.x for the combination of oxygen and nitrogen, where 0<x<1.