Microprocessor employing a technique for restoration of an aborted cycle

Abstract

A microprocessor is provided with an output pad logic circuit for each of its output lines. Each output pad logic circuit advantageously includes first and second latch circuits each configured to store output information at the same time. When the processor detects that a snoop write-back is pending, the second latch, referred to as a restore latch, preserves the information contained therein. During the snoop write-back operation, only the first latch stores the snoop write-back information and conveys the information to the output pins. When the snoop write-back operation is complete, an output enable signal is provided to the second latch to cause its stored information to be conveyed to the output pins upon the beginning of the next bus cycle. Subsequently, the second latch resumes capturing information along with the first latch. The output pad logic circuits within the microprocessor advantageously allow pipelined operations within the microprocessor and avoid the requirement of additional clock cycles to reload the output latch following a snoop write-back operation.