Srts clock recovery system implementing adaptive clock recovery

Abstract

An improved SRTS clock recovery system of a network node comprising a novel adaptifier arrangement that continually monitors the flow of data through a data FIFO and briefly assumes control over the SRTS clock recovery system to permanently adjust the phase and/or temporarily adjust the frequency of a transmit clock to avoid dataflow errors. Specifically, the adaptifier includes a phase controller that permanently adjusts a target phase offset utilized by the SRTS clock recovery system to effect a permanent change in the transmit clock phase. A frequency controller of the adaptifier temporarily overrides an error signal generated by the SRTS clock recovery system prior to it being utilized by a clock generator to effect a temporary adjustment of the transmit clock frequency. Clock perturbations are minimized, including graceful entry and exit of adaptifier action. The adaptifier implements either or both adjustments to avoid an impending dataflow error based upon a number of predetermined conditions. Once such an error is no longer anticipated, control is returned to the SRTS clock recovery system. Advantageously, data FIFO overflow and underflow conditions are prevented, thereby enabling the clock recovery system to provide error-free transmission through the implementing network node. The novel SRTS clock recovery system may make either temporary phase and/or permanent frequency adjustments to the transmit clock to recover from reference clock deviations without loss of data, without causing substantial perturbations in the transmit line frequency, while maintaining interoperability with existing SRTS equipment.