Static adder using bicmos emitter dot circuits

Abstract

A parallel static adder for adding two n-bit operands, the adder including half-sum circuitry, summing circuitry, and carry look-ahead circuitry. The half-sum circuitry receives a pair of same-order bits from the two n-bit operands, and generates a plurality of half-sum signals for each of the pairs of same-order bits. The summing circuit adds a corresponding half-sum signal to a carry signal from a preceding lower order summing circuit. The carry look-ahead circuit generates a carry signal for higher order summing circuits. Each of the carry look-ahead circuits includes a plurality of logic arrays, each comprising one or more field effect devices coupled in parallel between a first node and a second node, where each of the field effect devices has a gate input to receive lower order addend and augend bits in accordance with a predetermined carry look-ahead equation. The carry look-ahead logic further includes a plurality of bipolar devices, coupled in parallel between a supply voltage and an output node, where each has a base terminal coupled to one of the first nodes of the plurality of field effect devices to provide a sum term of the predetermined sum-of-products at the output node.