Integrated circuit memory devices including split word lines and

Abstract

An integrated circuit memory device includes a memory cell array including a plurality of odd and even numbered subword lines extending therethrough. A predecoder receives a row address and generates a plurality of predecoding signals in response thereto, and a row decoder receives the row address and generates a word line signal in response thereto. A first driver block includes a first plurality of word line drive circuits adjacent the memory cell array wherein each of the word line drive circuits of the first plurality is connected to a respective odd numbered subword line of the memory cell array. A first plurality of subword line drive circuits drive the respective odd numbered subword lines responsive to odd numbered predecoding signals and the word line signal. A second driver block includes a second plurality of word line drive circuits adjacent the memory cell array opposite the first driver block wherein each of the word line drive circuits of the second plurality is connected to a respective even numbered subword line of the memory cell array. The second plurality of subword line drive circuits drive the respective even numbered subword lines responsive to even numbered predecoding signals and the word line signal. Related methods are also disclosed.