The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 1998
Filed:
Feb. 29, 1996
Keniti Imamiya, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
First and second inverter circuits each include a P channel and an N channel MOS transistor whose current paths are connected in series between a power-supply and ground. An input terminal of the second inverter circuit is connected to an output terminal of the first inverter circuit. A first capacitor is connected between the output terminal of the second inverter circuit and the power supply. A second capacitor is connected between the output terminal of the first inverter circuit and ground. A third capacitor is connected between the output terminal of the second inverter circuit and the input terminal of the first inverter. A fourth capacitor is connected between the input terminal of the first inverter circuit and ground. When an output voltage of the first inverter circuit is in a low level state at time of the rise of the power supply and a charging voltage of the third capacitor reaches a threshold voltage of the P channel MOS transistor of the first inverter circuit, an output voltage of the first inverter circuit is set to a high level to charge the second capacitor. When an output voltage of the second inverter circuit rises in accordance with the power-supply voltage, and a charging voltage of the second capacitor reaches a threshold voltage of the N channel MOS transistor of the second inverter circuit, the output voltage of the second inverter circuit is set to a low level.