The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 1998

Filed:

Feb. 11, 1997
Applicant:
Inventors:

Dan Trong Tran, Laguna Niguel, CA (US);

Paul Bernard Ricci, Laguna Niguel, CA (US);

Jayesh Vrajlal Sheth, Mission Viejo, CA (US);

Theodore Curt White, Tustin, CA (US);

Richard Allen Cowgill, Lake Forest, CA (US);

Assignee:

Unisys Corporation, Blue Bell, PA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711141 ; 711142 ; 711143 ; 711144 ; 711145 ; 711146 ; 711119 ; 711120 ; 711129 ; 711173 ; 395308 ; 39580013 ;
Abstract

A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.


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