The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 1998
Filed:
Jan. 28, 1997
Randy Charles Steele, Folsom, CA (US);
Duane H Chinnow, Jr, Folsom, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A field programmable gate array (FPGA) includes a number of configurable function blocks, each separately configurable by the user of the FPGA as either high performance programmable logic or a block of SRAM. In accordance with the present invention, each configurable function block includes a volatile logic array comprised of an array of 'AND' gates and an array of 'OR' gates with programmable connections. The programmable connections in the volatile logic array comprise SRAM cells. These SRAM cells are then capable of serving the user of the FPGA in two modes of operation. In a first mode of operation, logic mode, the SRAM cells provide for the programmable connections which direct the logic operations in the volatile logic array. In a second mode of operation, memory mode, the SRAM cells function as a block of SRAM which can then be written to, and read from, using standard SRAM access signals.