Bus with high gross data transfer rate

Abstract

A pipelined bus which can support more than one channel between data sources and data destinations at a time. The bus includes an arbitration bus, a command bus and a data bus. In accordance with the bus protocol, different channels may access the various bus components in the same clock cycle. For example, the data source of one channel may issue a command on the command bus to its selected data destination to get ready to receive data while at the same time, a data source of a second channel actually transmits data on the data bus to its selected data destination. During the same clock cycle, a third data source can be selected by the arbitration bus to initiate or resume a channel. In the following clock cycle, the third data source can transmit a command on the command bus to its selected data destination to get ready to receive data, the second data source can transmit data on the data bus to its data destination and a fourth data source can be selected by the arbitration bus to initiate or resume a channel. In this manner, the set up and delivery of data for the different channels overlap in each clock cycle. Because a particular channel is not always ready to send or receive data, it has been found that such an arrangement increases the overall efficiency of the bus.