Semiconductor memory with built-in parallel bit test mode

Abstract

A semiconductor memory includes a plurality of primary memory cells arranged in a row and column matrix formed on a semiconductor chip area and a plurality of redundant memory cells which replace primary memory cells which are found to be defective. The semiconductor memory includes a first test circuit for simultaneously writing one data value to a first number of the primary memory cells and simultaneously reading stored data from the first number of the primary memory cells to determine whether all of the stored data have the same data value, thereby performing a first parallel bit test on the first number of the primary memory cells. The first parallel bit test is performed while the semiconductor memory is in a wafer state. The semiconductor memory also includes a second test circuit which performs a second parallel bit test on a second number of primary memory cells. The second number is equal to the number of redundant memory cells in a redundant memory cell replacement unit (a row or column of redundant memory cells). The second parallel bit test determines whether the second number of primary memory cells should be replaced by a redundant memory cell replacement unit.