Data reproduction apparatus

Abstract

A data reproduction apparatus includes a PR-equalizing circuit which equalizes data reproduction signals recorded on a recording medium based on a partial response system and produces output signals, a binary code circuit which changes output signals from the PR-equalizing circuit into binary signals, a clock generation circuit which generates clock signals synchronized to the edges of the binary signals, A/D converters which sample the output signals from the PR-equalizing circuit based on the clock signal and generates sample data, decoding circuits which decode the sample data based on a predetermined ideal amplitude value and generates reproduced data, and a synthesis circuit which synthesizes reproduced data from the decoding circuits. A second data reproduction apparatus includes an equalizing circuit which equalizes wave pattern reproduction signals by means of a partial response method, a binary code circuit which changes the wave pattern equalized reproduction signals into binary coded signals, a PLL circuit which generates clock signals synchronized with the edges of the binary coded signals, coding circuits which transform the wave pattern equalized reproduction signals into binary signals by means of the clock signals from the PLL circuits, and a synthesis circuit which synthesizes the binary signals from the coding circuits.