Semiconductor memory device having a defect relief arrangement

Abstract

In a semiconductor storage device wherein data lines connected to a plurality of memory cells selected by a select operation of word lines are sequentially selected by using an address signal generated by an address counter to serially read data in individual unit of at least one word line: redundancy data lines disposed perpendicular to the word lines are provided; a column select circuit receiving a Y address signal selects one of the data lines or redundancy data lines; a redundancy memory circuit stores, in the order of the selection operation by the column select circuit, a defect address signal of a defect data line among the data lines and a redundancy address signal of a corresponding redundancy data line; an address comparator circuit compares one defect address signal read from the redundancy memory circuit with an address signal generated by the address counter; an address signal for the redundancy memory circuit is generated by performing a count operation in response to a coincidence signal generated by the address comparator circuit; and the address signal generated by the address counter is replaced by a redundancy address signal read in response to the coincidence signal from the redundancy memory circuit and used as the Y address signal. Accordingly, a redundancy circuit of simple configuration can be obtained because only a single address comparator circuit is used.